1. Field
This disclosure generally relates to electronic design automation. More specifically, the disclosure relates to methods and apparatuses to execute processing stages of an electronic design automation work flow in an incremental and concurrent fashion.
2. Related Art
Rapid advances in computing technologies have been made possible by advances in electronic design automation (EDA) tools. The last step in the EDA flow is called mask synthesis, and reducing the turnaround time (TAT) for this step is critical. Foundries often impose stringent TAT requirements on EDA vendors. For example, a foundry may require that the TAT of the mask synthesis step be less than 12 hours.
Unfortunately, due to the rapid increase in the size and complexity of mask data, it is becoming increasingly difficult to meet such TAT requirements. Starting with a two-fold increase in design data volume per process generation, increasing RET (resolution enhancement technology) usage, more aggressive OPC (optical proximity correction), and unavoidable loss of hierarchy from long range-interactions, mask data volume is increasing many-fold per generation.
Specifically, I/O and resource contention are beginning to exhibit serious bottlenecks, throttling actual cycle times. For example, merely transferring one terabyte of layout data (expected at 32 nm process generation) to or from a hard disk drive can take about 3 hours with conventional hard disk drive technology. With multiple handoffs among processing stages, such as RET, OPC, MDP (mask data preparation), etc., the I/O time alone can exceed the TAT requirement. Hence, there is a need for techniques and systems to reduce the TAT for mask synthesis.